Livoa
Discord
Pricing
English
Sign In
Row Decoder
Control Block
Memory Core 128x128
Dummy Column
Bit Cells
Bit Cells
Dummy Row
128-Bit IO BLOCK
Self-Test IO Block
8-Bit IO BLOCK_1
8-Bit IO BLOCK_15
8-Bit IO_End BLOCK
Row Pre-decoder Circuit
2 to 4 Predecoder
2 to 4 Predecoder
3 to 8 Predecoder
Clock Generation Circuit
Read/Write Control Circuit
Precharge cells
Column Multiplexer
Column Decoder
Sense Amplifier
Data Input Circuit (write Driver)
Data Output Circuit
Precharge cells
Column Multiplexer
Column Decoder
Sense Amplifier
Data Input Circuit (write Driver)
Data Output Circuit
Precharge cells
Column Multiplexer
Column Decoder
Sense Amplifier
Data Input Circuit (write Driver)
Data Output Circuit
test
by asd
Use this design
0
0 uses