Verilog Source (.v)

Verilog Testbench (.v)

Standard Cell Models (.v)

Constraints (.tcl)

Standard Cell Library (see below)

TLU+ Files (.tluplus)

iverilog

VCS

Delay File (.sdf)

Timing & Area

Gate Level Netlist (.v)

Constraints File (.sdc)

RTL Simulator (.a.out)

RTL Simulator (simv)

Design Compiler

Design Vision GUI

IC Compiler