FullAdder_4bit

FullSubtractor_4bit

VedicMul_4bit

LogicGates4

op sel[3:0]

CLK

EN

0000 → sum

0001 → diff

0010 → mul

0011 → and_o

0100 → or_out

0101 → nand_o

0110 → nor_out

0111 → x_or_ou

1000 → xnor_ou

default → 8'b0

sum[4:0]

gated_clk

z[7:0]