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Fetch–Decode–Execute Cycle (CPU Architecture)
Processor (CPU)
Main Memory (RAM)
Memory Unit
MAR
MDR
Control Unit
PC
CIR
System Clock
ALU
ACC
Status Register
Mem Cell 1
Mem Cell 2
Mem Cell 3
Mem Cell 4
Address Bus
Data Bus
Control Bus
Check for Interrupts
FDE
by Codem1
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